The present invention relates to a nonvolatile semiconductor memory, a data deletion method of the nonvolatile semiconductor memory, an information processing apparatus and a nonvolatile semiconductor memory system. More particularly, the present invention relates to a technique effective to be applied to a nonvolatile semiconductor memory (EEPROM: Electric Erasable Programmable Read Only Memory) capable of electrically writing and deleting data.
An EEPROM represented by, for example, a flash memory includes a source and a drain which are formed on the surface of a well in a semiconductor substrate, a charge accumulation layer (or floating electrode) which is formed on the source and the drain through a gate insulating film, and a control electrode which is provided on the charge accumulation layer (or floating electrode) through an insulating film. The EEPROM determines data (xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d) which is held therein depending on whether or not electrons are injected into the charge accumulation layer (or floating electrode) (depending on the magnitude of the threshold value of each memory cell).
To write or delete data to and from this EEPROM, hot electrons which are generated by the potential difference between the control electrode of a selected memory cell and the semiconductor substrate (well, source or drain) or electrons which are emitted by a tunnel phenomenon are injected or pulled out into and from the charge accumulation layer (or floating electrode).
In the case where an operation for pulling out electrons from the charge accumulation layer (or floating electrode) of the EEPROM (flash memory) is defined as deletion, it is necessary to apply a high negative voltage (negative voltage having the high absolute value of the voltage) to the control electrode of a memory cell selected to secure the above-stated potential difference during this deletion.
However, if a high negative voltage (negative voltage having the high absolute value of the voltage) is applied to the control electrode, it is also required to increase the withstand voltage of an MISFET (Metal Insulator Semiconductor Field Effect Transistor) which constitutes peripheral circuits driving the control electrode. To increase the withstand voltage of the MISFET, it is necessary to make the gate insulating film thicker. If the gate insulating film becomes thicker, the driving capability of the MISFET is deteriorated and a read rate is eventually sacrificed.
To prevent this disadvantage, a technique for obtaining a desired potential difference while lowering a negative voltage applied to the control electrode (lowering the absolute value of the voltage) by applying a positive voltage to the well in the semiconductor substrate, is considered.
The inventors of the present invention have been dedicated to study and development related to nonvolatile semiconductor memories. After considering the above-stated technique, the inventors were faced with a problem regarding time required to reach a deletion potential (time required to pull out a desired quantity of electrons).
The inventors applied themselves closely to the cause of this problem. As a result, the inventors reached the conclusion that the problem is caused by the fact that the well is electrically separated from the semiconductor substrate and a parasitic capacitance is thereby generated in a separation region.
In other words, if a positive voltage is applied to the well in the semiconductor substrate, the well is electrically separated from the semiconductor substrate and a separation region opposite in conductive type to the well is thereby formed between the well and the semiconductor substrate. If data is deleted from the EEPROM (flash memory), it is required to charge a parasitic capacitance generated between the well and the separation region, the separation region and the semiconductor substrate, making deletion time (including time required until the voltage becomes a desired value) longer.
Furthermore, during data deletion, if it is determined whether or not the threshold voltage of a memory cell is a predetermined threshold voltage and it is found that the threshold voltage of the memory cell is higher than the desired threshold voltage, then the data is re-deleted so as not to apply an excessive stress (a series of these operations will be referred to as xe2x80x9ca deletion verification operationxe2x80x9d hereinafter).
While the threshold voltage of the memory cell is determined, the charged parasitic capacitance stated above should be discharged. In addition, if the data is re-deleted from the memory cell, the parasitic capacitance thus discharged should be charged again.
As can be seen, during the deletion verification discharged, with the result that the problem of the increase of deletion time becomes more serious.
It is an object of the present invention to provide a technique capable of shortening time required to delete data from a nonvolatile semiconductor memory such as an EEPROM (flash memory).
The above and other objects and the novel features of the present invention will be readily apparent from the description of the specification of the present application and accompanying drawings.
Among the inventions disclosed in the present application, typical inventions will be briefly outlined as follows.
(1) A nonvolatile semiconductor memory according to the present invention includes: a semiconductor substrate; a first semiconductor region; a second semiconductor region formed on the first semiconductor region; a memory cell section formed on the second semiconductor region; and a control section which outputs a control signal instructing a voltage generation section to generate a voltage applied to the second semiconductor region when or before receiving an access instruction from an outside indicating that it is necessary to charge the second semiconductor region, and which indicating a control signal for discharging the second semiconductor region when indicated from the outside to discharge the second semiconductor region, to the voltage generation section.
(2) A nonvolatile semiconductor memory according to the present invention includes voltage application means for applying a voltage to a second semiconductor region (NiSO) formed between a semiconductor substrate and a first semiconductor region in which a nonvolatile memory cell is formed, the means different from means for applying a voltage to the first semiconductor region.
(3) A nonvolatile semiconductor memory according to the present invention includes means for prohibiting a voltage from being applied to a second semiconductor region formed between a semiconductor substrate and a first semiconductor region in which a nonvolatile memory cell is formed.